Programmable gate array based on configurable metal interconnect vias
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United States of America Patent
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Oct 14, 2003
Grant Date -
Mar 6, 2003
app pub date -
Sep 5, 2001
filing date -
Sep 5, 2001
priority date (Note) -
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Abstract
A method is comprised of translating a bit stream defining the state of switches of an FPGA into a set of via geometries, or generating the set of via geometries directly from a physical design system. The via geometries are used to produce at least one via mask. The via mask is then used in a manufacturing process to customize an array of fixed and/or programmable logic blocks.
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