Fault-tolerant maintenance bus architecture
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United States of America Patent
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Oct 14, 2003
Grant Date -
N/A
app pub date -
Apr 13, 2000
filing date -
Apr 13, 2000
priority date (Note) -
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Abstract
A fault-tolerant maintenance bus architecture provides dual maintenance buses interconnecting each of a plurality of parent circuit boards. The two maintenance buses are each connected to a pair of system management modules (SMMs) that are configured to perform a variety of maintenance bus activities. Within each parent board are a pair of redundant bridges each having a unique address. One bridge is connected to the first maintenance bus while a second bridge is connected to the second maintenance bus of the pair. A child maintenance bus interconnects the two bridges one a child circuit board. The child maintenance bus is itself interconnected with a variety of monitor and control to functions on maintenance bus-compatible subsystem components. The SMMs can address components on each child board individually and receive appropriate responses therefrom. In the event of a bus failure, the other bus can still communicate with child subsystem components via the unaffected bridge.
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