Decoding circuit for memories with redundancy

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United States of America Patent

PATENT NO 6634003
SERIAL NO

09501807

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A system for disabling defective memory elements includes a memory array, an address decoder and a decoder element. The memory array has multiple memory elements for storing data. The address decoder receives a requested memory address and produces multiple element-select signals. Each element-select signal is associated with one of the memory elements and indicates whether access to the associated memory element is requested by the host. The decoder element receives one of the element-select signals and provides an output signal to the associated memory element. If the associated memory element is functional, the output signal enables or disables the associated memory element in accordance with the associated element-select signal. If, on the other hand, the associated memory element is defective, the output signal disables the associated memory element regardless of the associated element-select signal. The decoder element is programmed upon power-up so as not to require an address comparison for each memory access cycle.

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Patent Owner(s)

Patent OwnerAddress
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE LTDSINGAPORE SINGAPORE SINGAPORE CITY SINGAPORE

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Phan, Tuan Santa Clara, CA 17 273

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