Internal clock generating circuit for clock synchronous semiconductor memory device
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United States of America Patent
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Oct 21, 2003
Grant Date -
N/A
app pub date -
Apr 28, 1999
filing date -
May 1, 1998
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
To input buffers included in a peripheral pad group inputting an external signal and a DQ pad group for data input/output, clock signals from a synchronizing circuit are transmitted through a clock distributing circuit having a plurality of clock transmission nodes arranged in a shape of a tree. The synchronizing circuit accomplishes phase synchronization between a signal from a node nearest to the clock distributing circuit with an external clock signal. Thus, a skew in clock signals applied to the input and output buffers can be eliminated.
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