Decimated digital phase-locked loop for high-speed implementation
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United States of America Patent
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Oct 21, 2003
Grant Date -
Jun 20, 2002
app pub date -
Nov 21, 2001
filing date -
Nov 24, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
A phase lock loop to control phase error from a first input signal and a second input signal including a phase error detector to detect a phase error signal between the first input signal and the second input signal at a predetermined rate, a down-sampling circuit to down-sample the phase error signal and to output a down-sampled signal at a reduced rate with respect to the predetermined rate, a loop filter to filter the down-sampled signal to obtain a filtered signal, and an up-sampling circuit to up-sample the filtered signal at the predetermined rate.
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