Importance

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Abstract

A Thin Film Transistor (TFT) array substrate has a dummy signal line as a short circuit wiring for preventing a short circuit due to electrostatic breakdown between a signal line as an upper layer wiring and a gate line as a lower wiring. The dummy signal line is formed on an outer peripheral area of the TFT array substrate. This dummy signal line has a three-layer structure of a silicon lower layer, an Indium Tin Oxide (ITO) intermediate layer and an aluminum (Al) upper layer, enumerated from the lower layer. Although the silicon layer is formed as one consecutive wiring during formation thereof, the silicon layer is etched simultaneously with the Al layer when the Al layer is subjected to pattern forming, and is electrically disconnected between the gate lines. Since the dummy wiring is disconnected after its formation, a short circuit does not occur between the gate lines even in the case where the dummy wiring and two or more of the gate lines are short-circuited with each other.

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First Claim