Importance

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Abstract

A method and apparatus for synchronizing components operating isochronously that are coupled by independent links. The apparatus includes a synchronization circuit having a first and second buffer, each including an input port coupled to an external link, an output port, a read pointer and a write pointer. The read pointer indicates a next location in a respective buffer to be read in transferring data out on the output port. The write pointer indicates a next location in the respective buffer to be written when receiving data on the input port and is configured to automatically increment upon receipt of a first data bit on a respective external link. A trigger circuit is coupled to each link for receiving external trigger signals. Each external trigger signal is included along with data transmitted on the link and indicates when data is present on a respective link. A counter is coupled to the trigger circuit. The counter includes a trigger input and a predefined delay period. After receipt of a first of the external trigger signals on the trigger input, the counter is operable to output a read enable signal to each of the read pointers after the delay period has expired.

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First Claim