Coherency for DMA read cached data
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United States of America Patent
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Oct 21, 2003
Grant Date -
N/A
app pub date -
Aug 24, 2000
filing date -
Aug 24, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
A method and implementing computer system are provided which enable a process for implementing a coherency system for bridge-cached data which is accessed by adapters and adapter bridge circuits which are normally outside of the system coherency domain. An extended architecture includes one or more host bridges. At least one of the host bridges is coupled to I/O adapter devices through a lower-level bus-to-bus bridge and one or more I/O busses. The host bridge maintains a buffer coherency directory and when Invalidate commands are received by the host bridge, the bridge buffers containing the referenced data are identified and the indicated data are invalidated.
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