US Patent No: 6,638,831

Number of patents in Portfolio can not be more than 2000

Use of a reference fiducial on a semiconductor package to monitor and control a singulation method

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ATTORNEY / AGENT: (SPONSORED)
 

Importance

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Abstract

A semiconductor package singulation process is disclosed. The process comprises the step of using at least a portion of a reference fiducial formed on at least one package in a semiconductor package panel comprising a plurality of interconnected packages, the fiducial used to monitor and to control the semiconductor package singulation process.

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First Claim

Related Publications

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Patent Owner(s)

Patent OwnerAddressTotal Patents
MICRON TECHNOLOGY, INC.BOISE, ID18599

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chapman, Gregory M Meridian, ID 31 168
Drussel, Zane Boise, ID 6 31
Roberts, Jay Meridian, ID 3 6
VanNortwick, John Kuna, ID 37 160

Cited Art

Patent Info (Count) # Cites Year
 
MICRON TECHNOLOGY, INC. (40)
4,977,993 Out-of-tube inspection part holder 4 1989
4,973,948 Reversed or missing lead frame detector 9 1990
5,279,975 Method of testing individual dies on semiconductor wafers prior to singulation 90 1992
5,375,320 Method of forming "J" leads on a semiconductor device 40 1992
5,483,741 Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice 275 1994
6,072,236 Micromachined chip scale package 230 1996
5,831,445 Wafer scale burn-in apparatus and process 19 1996
6,049,977 Method of forming electrically conductive pillars 15 1997
6,084,311 Method and apparatus for reducing resin bleed during the formation of a semiconductor device 18 1997
6,040,702 Carrier and system for testing bumped semiconductor components 98 1997
6,013,535 Method for applying adhesives to a lead frame 16 1997
6,336,973 Apparatus and method for modifying the configuration of an exposed surface of a viscous fluid 3 1997
6,096,165 Method and apparatus for application of adhesive tape to semiconductor devices 6 1997
6,047,470 Singulation methods 9 1997
6,048,744 Integrated circuit package alignment feature 131 1997
5,961,722 Apparatus for establishing reference coordinates for a point on a component 9 1997
6,018,249 Test system with mechanical alignment for semiconductor chip scale packages and dice 148 1997
6,025,212 Method for attaching semiconductor dice to lead-on-chip leadframes 20 1998
6,158,647 Concave face wire bond capillary 28 1998
6,329,832 Method for in-line testing of flip-chip semiconductor assemblies 17 1998
6,006,739 Method for sawing wafers employing multiple indexing techniques for multiple die dimensions 33 1999
6,321,739 Film frame substrate fixture 5 1999
6,242,271 Method for establishing reference coordinates for a point on a component 3 1999
6,267,167 Method and apparatus for application of adhesive tape to semiconductor devices 5 1999
6,281,044 Method and system for fabricating semiconductor components 16 1999
6,239,380 Singulation methods and substrates for use with same 14 1999
6,346,152 Method and apparatus for applying adhesives to a lead frame 5 1999
6,397,715 Slug-retaining punch press tool 4 1999
6,368,897 Method for manufactoring and using stencil/screen 4 2000
6,521,287 Method for manufacturing improved stencil/screen 4 2000
6,537,400 Automated method of attaching flip chip devices to a substrate 9 2000
6,485,778 Method of applying an adhesive material to lead fingers of a lead frame 2 2000
6,369,602 Method for in-line testing of flip-chip semiconductor assemblies 2 2000
6,311,890 Concave face wire bond capillary 11 2000
6,245,646 Film frame substrate fixture 19 2000
6,545,498 Method for in-line testing of flip-chip semiconductor assemblies 2 2001
6,440,777 Method of depositing a thermoplastic polymer in semiconductor fabrication 13 2001
6,544,803 Method for determining the concentration of contamination on a component 3 2001
6,439,450 Concave face wire bond capillary 10 2001
6,472,901 Method for in-line testing of flip-chip semiconductor assemblies 2 2001
 
OKI SEMICONDUCTOR CO., LTD. (3)
5,496,777 Method of arranging alignment marks 21 1994
5,641,113 Method for fabricating an electronic device having solder joints 145 1995
6,303,470 Semiconductor wafer and method for manufacturing semiconductor devices 8 2000
 
ROUND ROCK RESEARCH, LLC (3)
5,674,785 Method of producing a single piece package for semiconductor die 341 1995
6,083,820 Mask repattern process 27 1998
6,048,755 Method for fabricating BGA package using substrate with patterned solder mask open in die attach area 226 1998
 
INTEL CORPORATION (2)
5,942,805 Fiducial for aligning an integrated circuit die 15 1996
6,001,703 Method of forming a fiducial for aligning an integrated circuit die 11 1997
 
NATIONAL SEMICONDUCTOR CORPORATION (2)
5,923,995 Methods and apparatuses for singulation of microelectromechanical systems 103 1997
6,049,974 Magnetic alignment apparatus and method for self-alignment between a die and a substrate 5 1998
 
RENESAS ELECTRONICS CORPORATION (2)
5,777,392 Semiconductor device having improved alignment marks 25 1996
5,716,889 Method of arranging alignment marks 9 1996
 
ACC MICRO, INC. (1)
5,703,402 Output mapping of die pad bonds in a ball grid array 18 1995
 
AGERE SYSTEMS INC. (1)
6,043,670 Method for testing integrated circuits 7 1997
 
AMKOR TECHNOLOGY, INC. (1)
6,020,218 Method of manufacturing ball grid array semiconductor package 33 1998
 
DENSO CORPORATION (1)
6,081,040 Semiconductor device having alignment mark 13 1998
 
FUJI MACHINERY MFG. & ELECTRONICS CO., LTD. (1)
6,011,694 Ball grid array semiconductor package with solder ball openings in an insulative base 119 1997
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
5,880,590 Apparatus and method for burn-in and testing of devices with solder bumps or preforms 54 1997
 
KABUSHIKI KAISHA TOSHIBA (1)
6,101,148 Dynamic random access memory 4 1997
 
LEAR CORPORATION (1)
5,703,303 Method and system for wear testing a seat by simulating human seating activity and robotic human body simulator for use therein 9 1996
 
LSI LOGIC CORPORATION (1)
5,729,894 Method of assembling ball bump grid array semiconductor packages 105 1996
 
MAGNACHIP SEMICONDUCTOR, LTD. (1)
6,072,700 Ball grid array package 20 1998
 
MEDIX CORPORATION (1)
6,012,502 Apparatus for attaching adhesive tape to lead-on-chip leadframes 32 1997
 
NEC CORPORATION (1)
6,078,506 Tape-ball grid array type semiconductor device having reinforcement plate with slits 13 1998
 
NIKON CORPORATION (1)
5,859,707 Position detection apparatus and aligner comprising same 16 1997
 
NORWEST BANK MINNESOTA, NATIONAL ASSOCIATION (1)
4,478,352 Integrated circuit component handler singulation apparatus 27 1982
 
ROBERT BOSCH GMBH (1)
6,054,338 Low cost ball grid array device and method of manufacture thereof 12 1998
 
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (1)
5,904,555 Method for packaging a semiconductor device 10 1998
 
ULTRATECH, INC. (1)
5,872,051 Process for transferring material to semiconductor chip conductive pads using a transfer substrate 82 1995
 
XEROX CORPORATION (1)
5,668,061 Method of back cutting silicon wafers during a dicing procedure 29 1995

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
STMICROELECTRONICS S.R.L. (3)
7,348,682 Method and structures for indexing dice 3 2005
7,491,620 Method and structures for indexing dice 0 2008
7,868,474 Method and structures for indexing dice 1 2009
 
ADVANCED MICRO DEVICES, INC. (1)
7,030,772 Inspection for alignment between IC die and package substrate 4 2004
 
TEXAS INSTRUMENTS INCORPORATED (1)
7,171,035 Alignment mark for e-beam inspection of a semiconductor wafer 0 2002

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
11.5 Year Payment $7400.00 $3700.00 $1850.00 Apr 28, 2015
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Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00