Defect avoidance in an integrated circuit
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United States of America Patent
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Oct 28, 2003
Grant Date -
Jun 27, 2002
app pub date -
Oct 3, 2001
filing date -
Oct 6, 2000
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A method of using an integrated circuit with at least one defect, said method comprising the steps of determining the location of one or more defects in said integrated circuit; selecting a program to be stored on said integrated circuit, said program being selected on the basis of the location of said one or more defects; and loading said program onto said integrated circuit.
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