Wire bonding method and semiconductor package manufactured using the same
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United States of America Patent
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Nov 4, 2003
Grant Date -
May 30, 2002
app pub date -
Dec 20, 2000
filing date -
Dec 20, 1999
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor package including plural semiconductor chips, and a wire bonding step for electrically interconnecting the semiconductor chips, are disclosed. In an exemplary method, a substrate is provided. Conductive circuit patterns are provided outside of a chip mounting region of the substrate, and conductive transfer patterns are provided proximate to the chip mounting region. Chips are placed in the chip mounting region. Conductive wires are bonded between input/output pads of a first chip and respective transfer patterns, and other conductive wires are bonded between input/output pads of a second chip and the same transfer patterns, thereby electrically connecting respective input/output pads of the two chips through a pair of bond wires and an intermediate transfer pattern.
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