Bit line decoding scheme and circuit for dual bit memory with a dual bit selection
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United States of America Patent
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Nov 4, 2003
Grant Date -
Feb 13, 2003
app pub date -
Jul 8, 2002
filing date -
Jul 6, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In the present invention a bit line decoder scheme is described that connects data and voltage to a plurality of bit lines of a dual bit flash memory array. The bit lines are connected to a plurality of intermediate data lines by a first decoder unit and the intermediate data lines are connected to a plurality of data lines of the sense amplifiers by a second decoder unit. In one embodiment the voltage is connected to a selected bit line through a separate decoder unit and in a second embodiment the voltage is connected through the decoder unit connected to the intermediate data lines.
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