Apparatus and method for refresh and data input device in SRAM having storage capacitor cell
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United States of America Patent
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Nov 4, 2003
Grant Date -
Apr 24, 2003
app pub date -
Mar 7, 2002
filing date -
Oct 23, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
An apparatus for a refresh and a data input device in the SRAM having a storage capacitor cell comprises an internal clock generator for generating and outputting two internal clock signals having a certain time difference of each other, a refresh timer for generating and outputting an output signal to notify a refresh time, a refresh signal generator for generating a refresh signal in response to a faster signal of the two internal signals and the output signal from the refresh timer, a refresh counter for generating refresh addresses during the refresh and a column path controller for controlling the activation of a column path in response to a row active signal and the refresh signal.
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