Asynchronous queuing circuit for DRAM external RAS accesses
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United States of America Patent
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-
Nov 4, 2003
Grant Date -
N/A
app pub date -
Aug 2, 2002
filing date -
Aug 2, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and queuing circuit are provided for storing asynchronous external RAS access requests and for executing corresponding RAS cycles. When no current external access RAS cycle is currently underway a first request latch or similar storage element is set in response to an initial access request. When access to the memory begins in a RAS cycle, this first request latch is reset. When a RAS cycle is currently underway, a second request-queuing latch is set in response to a new, second access request that occurs. Whenever a RAS cycle is completed, if the second queuing latch is set, a new RAS cycle is initiated and both the first and the second latches are reset. Any subsequent new access request may then be queued if the subsequent new access request arrives prior to completion of the current second access cycle.
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