Method and system for efficient cache memory updating with a least recently used (LRU) protocol
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Nov 4, 2003
Grant Date -
N/A
app pub date -
Mar 20, 2000
filing date -
Mar 20, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method of and system for concurrently processing multiple memory requests. The first and second memory requests contain a linear address. A search for the cache entry in a cache block is issued in response to the linear address. After locating the cache entries associated with the memory requests, there is an update of the least recently used status for the cache entries with reference to the memory requests.
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