Transceiver with latency alignment circuitry
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United States of America Patent
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Nov 4, 2003
Grant Date -
N/A
app pub date -
Dec 9, 1999
filing date -
Dec 9, 1999
priority date (Note) -
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Importance
Abstract
A transceiver system is described. A secondary memory module is coupled to a primary channel for receiving data and signals from a controller. The secondary memory module comprises a memory and a secondary channel for transmitting the data and control signals to the memory. The secondary memory module further comprises a transceiver coupled to the primary channel and the secondary channel. The transceiver is designed to electrically isolate the secondary channel from the primary channel. The transceiver is a low latency repeater to permit the data and the control signals from the controller to reach the memory, such that a latency of a data request from the controller is independent of a distance of the transceiver from the controller.
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