Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack
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United States of America Patent
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Nov 11, 2003
Grant Date -
Aug 21, 2003
app pub date -
Feb 20, 2002
filing date -
Feb 20, 2002
priority date (Note) -
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Abstract
A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.
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