PLL circuit including a control logic circuit for adjusting the delay times of the clocks so that the phase error of the clocks is reduced
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United States of America Patent
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-
Nov 11, 2003
Grant Date -
Jun 26, 2003
app pub date -
May 9, 2002
filing date -
Dec 21, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
VDLs and delay an input clock and a return clock and provide a delayed input clock and a delayed return clock to a PLL part. The PLL part receives the delayed input clock and the delayed return clock, and outputs a PLL output so that these signals are synchronous with each other. This PLL output finally returns as a return clock via an external circuit. A PD detects a phase difference between the input clock and the return clock, and outputs a phase comparison signal. A control logic circuit determines a degree of phase advance of the return clock with respect to the input clock based on the phase comparison signal, and controls a delay time of the VDL so that a phase error between the input clock and the return clock is zero.
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