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Abstract

An RF equalizer is implemented using a voltage divider L-attenuator. The RF equalizer provides a frequency variable compensation attenuation and generally includes a series impedance and an impedance to ground (i.e., a shunt impedance). The primary components of the series and shunt impedances are resistances. Preferably, the series impedance also includes a parallel combination of a bypass circuit (e.g., a series inductance and capacitance) and an augmenting circuit (e.g., a capacitor), while the shunt impedance is formed from a series RLC circuit. The bypass circuit, when implemented as a series LC resonant circuit, is preferably tuned to present a minimal impedance (i.e., a short or bypass) around the series resistance at the highest frequency of interest (e.g., 1000 MHz). At frequencies below resonance, the bypass circuit provides a net capacitive reactance which is augmented by the fixed capacitor in the augmenting circuit. In other words, the augmenting circuit presents an additional capacitance in parallel with the net capacitive reactance of the bypass circuit. The series impedance decreases with increasing frequency (and is virtually shorted out at the highest frequency of interest), thereby providing a frequency variable compensation attenuation with desired properties.

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