Methods and structure for read data synchronization with minimal latency
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United States of America Patent
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Nov 11, 2003
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N/A
app pub date -
Dec 5, 2001
filing date -
Dec 5, 2001
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Abstract
Methods and associated structure for realignment of returned read data from the memory component to the memory controller to adjust for phase shift in the memory device's supplied strobe signals due to propagation delays and other layout, fabrication and environmental factors. The realignment features of the present invention impose a calibrated delay on the memory controller's clock signal used to sample registered read data from the memory components. By so adjusting the alignment of returned read data with respect to the memory controller's clock, the present invention obviates the need for an asynchronous FIFO as is presently commonly practiced in the art to avoid such phase shifts between memory components and associated memory controller's.
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