Semiconductor memory device shiftable to test mode in module as well as semiconductor memory module using the same
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United States of America Patent
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Nov 11, 2003
Grant Date -
Feb 20, 2003
app pub date -
Mar 12, 2002
filing date -
Aug 8, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A DRAM includes a test mode circuit. Test mode circuit generates respective test mode signals of an L level and an H level by detecting first and second power supply voltages in response to first and second test mode shift signals, respectively. A control circuit controls peripheral circuits to input and output data for executing a special test to and from a plurality of memory cells in response to receiving of the test mode signals of an L level and an H level. Consequently, a semiconductor memory device can enter the test mode in a module.
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