Low power type Rambus DRAM
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Nov 11, 2003
Grant Date -
Jan 30, 2003
app pub date -
Jul 26, 2002
filing date -
Jul 27, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Disclosed is low power type Rambus DRAM including top/bottom memory bank units respectively comprising a plurality of banks for storing data, top and bottom serial/parallel shifter units, an interface logic circuit unit, a delay lock loop (DLL) unit and an input/output block unit. The top serial/parallel shifter unit is connected between the top memory bank unit and the input/output block unit and the bottom serial/parallel shifter unit is connected between the bottom memory bank unit and the input/output block unit. The interface logic circuit unit generates a signal for selecting the top or the bottom memory bank unit according to read or write command received from the external. The DLL unit generates a clock signal according to the signal outputted from the interface logic circuit unit. The input/output block unit generates a signal for selectively controlling the operation of top and bottom serial/parallel shifter units by buffering the clock signal generated from the DLL unit.
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