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Abstract

A congestion control mechanism in an ATM network access device includes segmentation and reassembly (SAR) logic that sends and receives Asynchronous Transfer Mode (ATM) cells to and from interface logic that transfers the cells to and from a switch fabric. The cells are transferred on ATM connections, including flow-controlled connections for which the sending of cells by the SAR logic is controlled in response to the settings of Generic Flow Control (GFC) bits appearing in the headers of ATM cells received by the SAR logic. The interface logic receives a congestion signal indicative of the level of congestion in a transmit buffer in the switch fabric. In response to the congestion signal, the interface logic sets the GFC bits in the headers of cells transferred to the SAR logic such that the cell transmission rate is maintained at a high average level while undesirable congestion in the transmit buffer is avoided. Hysteresis is employed in the setting of the GFC bits is response to the congestion signal. The interface logic generates idle cells during periods in which no traffic-carrying cells are being transferred from the switch fabric to the SAR logic, and sends the idle cells to the SAR logic to provide GFC signalling during such periods.

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