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Abstract

The invention discloses methods of fabricating a semiconductor device structure having low source/drain junction capacitances and low junction leakage currents. The low source/drain junction capacitances are obtained by implementing in a self-aligned manner the major portions of the heavily-doped source and drain regions of a device over the trench-isolation region using highly-conductive silicided polycrystalline-or amorphous-semiconductor and the junction leakage currents resulting from the generation/recombination current in the depletion regions of the heavily-doped source and drain junctions due to the implant-induced defects can be much reduced or eliminated. Moreover, the contacts are made on the silicided heavily-doped source and drain regions over the trench-isolation regions, the traditional contact-induced leakage current due to the shallow source/drain junction can be completely eliminated by the present invention. In addition, the contacts are implemented over the trench-isolation regions, the effective area per device is much reduced by using the present invention as compared to existing device structure and its implementation. As a consequence, the present invention offers a semiconductor device structure for high-density and high-performance integrated-circuits implementation.

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First Claim