Semiconductor memory module and register buffer device for use in the same
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United States of America Patent
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Nov 18, 2003
Grant Date -
Feb 6, 2003
app pub date -
Jun 25, 2002
filing date -
Aug 1, 2001
priority date (Note) -
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Abstract
In a semiconductor memory module having a plurality of DRAMs, when an input command is detected as a refresh command according to external control signals externally input for command-execution to a register buffer, internal control signals for a partial number of the DRAMs preliminarily selected among the plurality of DRAMs are delayed. Thus, the refresh command is executed with a time difference, and the semiconductor memory module prevents the plurality of dynamic semiconductor memories from simultaneously entering refresh modes to cause a great peak current to flow, and thereby implementing a stable operation.
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