Importance

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Abstract

A snapshot arbiter system for servicing multiple interrupt requests for a central processing unit (CPU) in a digital processor system, and for providing interrupts to the CPU corresponding to the interrupt requests. The system includes a synchronizer adapted to synchronize interrupt requests to a clock as they are received, and an interrupt masker adapted to receive a set of indicators identifying interrupt requests to be masked and to output active indicators that are a set of active interrupt request values corresponding to received interrupt requests that are not masked. Also included is a priority encoder block adapted to receive a set of priority values for respective interrupt requests and to provide as an output priority indicators that are a set of codes representing the priority values. A snapshot enable block is included, adapted to store enable indictors that are a set of bits representing currently enabled interrupt requests, and output those bits as enable bits. Also included is a snapshot register adapted to receive the active indicators and the enable indicators, and to output snapshot indicators that are a set of values representing the currently active and enabled interrupts. An interrupt generation block is included, adapted to receive the snapshot indicators and the priority indicators, and to output an interrupt corresponding to a highest priority interrupt request, to output a highest indicator representing a highest interrupt priority level in the snapshot register, and to output for reading by the CPU an identification indicator representing a currently selected interrupt request. Finally, an interrupt preemption block is included, adapted to receive the priority indicators, the active indicators and the highest indicator, and to output to the snapshot enable block a set of bits corresponding to each current interrupt request higher in priority than all of the interrupt requests represented in the snapshot register, for updating the snapshot enable block.

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First Claim