US Patent No: 6,651,230
Number of patents in Portfolio can not be more than 2000
Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design
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Nov 18, 2003
Issued date -
Dec 7, 2001
filing date -
09/683,276
serial no -
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Abstract
A method for reducing the effect of signal skew degradation in the design of an integrated circuit is provided. First, a circuit design library is created describing library cells as a function of one or more environmental variable, wherein the one or more environmental variable includes a skew degradation variable indicating skew degradation of a signal as a function of a total number of signal switches of the signal. Then, the integrated circuit design is modeled utilizing the circuit design library to determine a first skew degradation for each of the first and second signals at a first predetermined number of signal switches, and a second skew degradation for each of the first and second signals for a second predetermined number of signal switches, and further to determine a first relative skew degradation for a first predetermined number of signal switches and a second relative skew degradation for a second predetermined number of signal switches, wherein a relative skew degradation is equal to the difference of the skew degradation of the first signal and the skew degradation of the second signal for a given number of signal switches. Next, a skew shift equal to the difference between the first relative skew degradation and the second relative skew degradation is calculated. Finally, the integrated circuit design is modified such that a skew degradation of the first signal at the first predetermined number of signal switches is determined to be equal to the first skew degradation of the first signal minus half of the skew shift.
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First Claim
Related Publications
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 5,467,464 Adaptive clock skew and duty cycle compensation for a serial data bus | 59 | 1993 | |
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| 5,828,250 Differential delay line clock generator with feedback phase control | 38 | 1996 | |
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| 5,638,019 Accurately generating precisely skewed clock signals | 16 | 1995 | |
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| 6,024,478 Design aiding apparatus and method for designing a semiconductor device | 13 | 1996 | |
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| 5,656,963 Clock distribution network for reducing clock skew | 46 | 1995 | |
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| 5,896,299 Method and a system for fixing hold time violations in hierarchical designs | 23 | 1995 | |
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| 5,329,188 Clock pulse measuring and deskewing system and process | 26 | 1991 | |
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| 4,833,695 Apparatus for skew compensating signals | 44 | 1987 | |
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| 5,377,205 Fault tolerant clock with synchronized reset | 12 | 1993 | |
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| 5,163,068 Arbitrarily large clock networks with constant skew bound | 12 | 1991 | |
Patent Citation Ranking
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | May 18, 2015 |
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |