Circuit and method for reducing voltage stress in a memory decoder
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United States of America Patent
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Nov 25, 2003
Grant Date -
N/A
app pub date -
Dec 20, 2001
filing date -
Dec 20, 2001
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A circuit for generating an output signal, such as a subword line signal, to one or more memory cells of a memory. In one embodiment, the circuit includes four transistors each with a separate select line. In one example, a first switch is provided and has an input coupled with a global word line input signal; a second switch has an input coupled with the output of the first switch at an output node; a third switch has an input coupled with the global word line input signal and the output of the third switch being coupled with the output of the first switch at the output node; and a fourth switch having an input coupled with the output of the third switch at the output node and the output of the fourth switch is coupled with the output of the second switch.
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