Importance

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Abstract

A method, data processing system, and I/O subsystem suitable for authorizing DMA accesses requested by a 64-bit I/O adapter are disclosed. The system includes one or more processors that have access to a system memory. A host bridge is connected between the processor(s) and an I/O bus. A first I/O adapter, which generates 32-bit addresses, is coupled to the host bridge. A second I/O adapter coupled to the host bridge is enabled to generate an address with a width greater than 32-bits (such as a 64-bit address). The system may include a Translation Control Entry (TCE) table, that is configured with information needed to translate an address generated by the 32-bit adapter to a wider address (such as a 64-bit address). In addition, the TCE may determine whether DMA access to the translated address by the requesting adapter is authorized. The system further includes an Access Control Table (ACT). The ACT determines whether DMA access to the address generated by the 64-bit I/O adapter is authorized. The ACT may be formatted as a set of ACT entries where each ACT entry corresponds to a unique portion of the system's memory address space. In one embodiment, each ACT entry consists of a single bit that indicates access to a 256 MB or larger portion of the system memory address space. In one embodiment, the I/O bus is a PCI bus. The first and second I/O adapters may be connected to a secondary PCI bus that communicates with the primary PCI bus via a PCI-to-PCI bridge. In one embodiment, each 64-bit I/O adapter has its own ACT table and portions of the ACT table may reside in the PCI-to-PCI bridge.

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First Claim