Importance

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Abstract

An interrupt controller, ASIC, and electronic equipment are provided that make it possible to branch directly to interrupt processing routines at a plurality of locations. When an interrupt controller receives one of IR0 to IR31, it generates an IRQ for a CPU; traps an address AD from the CPU; and after determining that a read instruction for an interrupt vector has been executed, it generates a vector table address VTA corresponding to the interrupt factor with respect to a memory in which the interrupt vector table is stored. The CPU and the memory are connected to a higher-performance ASB, the interrupt controller is connected to a lower-performance APB. A selector selects one of the AD and the VTA, based on a signal from the interrupt controller. A first mode in which the VTA is generated and a second mode in which the interrupt vector is read are switchable.

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First Claim