Chip scale package in which layout of wiring lines is improved
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
Dec 2, 2003
Grant Date -
N/A
app pub date -
Oct 5, 2000
filing date -
Oct 5, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A semiconductor device of the present invention includes: a semiconductor chip having an electrode at a periphery thereof, a wiring board having a first surface and a second surface, the first surface of the wiring board being attached to the semiconductor chip, the board having an opening to expose the electrode of said semiconductor chip, and an external terminal arranged on the second surface of the wiring board and arranged inside of the wiring board compared with the opening. The semiconductor device has a wiring line laid on the second surface of the wiring board to electrically connect the electrode and the external terminal. The wiring line extends outside of said wiring board from the external terminal and detours said opening to reach the electrode.
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