Conditional clock buffer circuit
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United States of America Patent
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-
Dec 2, 2003
Grant Date -
Jun 26, 2003
app pub date -
Jan 22, 2003
filing date -
Sep 24, 2001
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a second transistor coupled to the precharge circuit via the first node and the second node, a third transistor coupled to the first transistor and the second transistor. The first transistor may be activated responsive to a condition external to the clock buffer circuit. When the first transistor is activated, an output clock signal driven by the clock buffer circuit may be inhibited.
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