Compensation model and registration simulation apparatus and method for manufacturing of printed circuit boards
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United States of America Patent
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Dec 2, 2003
Grant Date -
N/A
app pub date -
Mar 15, 1999
filing date -
Mar 15, 1999
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Methods and apparatuses are provided for modeling the compensation error and simulating registration error of a multilayer printed circuit board. Experiments are conducted in order to model compensation error which factor one or a combination of the following: the dielectric layer, the position of the core in the stack, the circuit configuration, the assembly of the printed circuit board, and the interaction between the core and the dielectric layer. The registration simulator combines the sources of registration error in an interdependent manner so as to model overall registration error over the panel surface.
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