Priority based simultaneous multi-threading
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United States of America Patent
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-
Dec 2, 2003
Grant Date -
Dec 27, 2001
app pub date -
Jul 8, 1997
filing date -
Jul 8, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A simultaneous multi-threaded architecture combines OS priority information with thread execution heuristics to provide dynamic priorities for selecting thread instructions for processing. The dynamic priority of a thread is determined by adjusting a heuristic measure of the thread's execution dynamics with a priority-dependent scaling function determined from the OS priority of the thread. An SMT processor includes logic for calculating a scaling function for each thread scheduled on the processor, tracking the threads' heuristics, and combing the scaling function and heuristic information into a dynamic priority for each thread. Instructions are selected for execution from among the scheduled threads according to the threads' dynamic priorities.
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