Importance

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Abstract

Methods and apparatus for a memory system using a ring memory bus architecture are disclosed. In one embodiment, a primary memory controller maintains point-to-point bus connections with each of two memory modules; the two modules maintain a third point-to-point bus connection between themselves, such that the three connections together form a ring bus. When data is sent from the controller to a module, half of the data is sent to the module in one direction along the ring and half is sent in the other direction, through the other module. Reverse bus communications from the module to the controller follow the reverse of these paths. This allows the bus to be half the width as it would otherwise be. In an alternate embodiment, each module contains two banks of memory that are arranged in a second ring bus local to the module. This can double the density of devices mounted on a module, while reducing pin count and simplifying signal routing on the module.

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First Claim