Automated system-on-chip integrated circuit design verification system
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 2, 2003
Grant Date -
May 15, 2003
app pub date -
Oct 3, 2001
filing date -
Oct 3, 2001
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Disclosed is a method of verifying the design of an integrated circuit chip comprised of one or more cores, comprising: creating a project core catalog comprising driver description files and application description files for each core; creating a system definition file for the integrated circuit chip; inputting the driver description files, the application description files and the system definition files into a code generator, the code generator outputting a test operating system test code; and applying the test operating system test code to a software simulation of the integrated circuit chip to perform design verification.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully