Importance

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Abstract

A synchronization circuit performs bit-to-bit timing correction of respective digital signals in digital signal packets applied to a packetized memory device. Each digital signal packet includes a plurality of digital signals applied to respective latches in the packetized memory device. A clock generator circuit generates a plurality of internal clock signals responsive to the external clock signal, each internal clock signal having a corresponding phase relative to the external clock signal. A plurality of selection circuits are coupled to the clock generator circuit and each has an output coupled to a clock terminal of an associated latch. Each selection circuit applies one of the internal clock signals to clock the associated latch in response to a phase command signal. An evaluation circuit receives digital signals sequentially stored in a selected one of the latches and generates a results signal indicating whether each of the digital signals has an expected value. A control circuit sequentially selects the latches and operates for each selected latch to adjust the phase command signals applied to the selection circuit coupled to the selected latch and store respective results signals sequentially received from the evaluation circuit for each phase command signal. The control circuit generates a final phase command signal from the stored results signals and applies each final phase command signal to the corresponding selection circuit Each of the final phase command signals adjusts the phase of clock signal applied to the associated latch relative to the digital signal applied to the latch so that the digital signal is successfully captured responsive to the clock signal.

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First Claim