Integrated circuits and methods for their fabrication

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6664129
APP PUB NO 20030085460A1
SERIAL NO

10318833

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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To fabricate contacts on a wafer backside, openings (124) are formed in the face side of the wafer (104). A dielectric layer (140) and some contact material (150), e.g. metal, are deposited into the openings. Then the backside is etched until the contacts (150C) are exposed and protrude out. The protruding portion of each contact has an outer sidewall (150V). At least a portion of the sidewall is vertical or sloped outwards with respect to the opening when the contact is traced down. The contact is soldered to an another structure (410), e.g. a die or a PCB. The solder (420) reaches and at least partially covers the sidewall portion which is vertical or sloped outwards. The strength of the solder bond is improved as a result. The dielectric layer protrudes around each contact. The protruding portion (140P) of the dielectric becomes gradually thinner around each contact in the downward direction. The thinned dielectric is more flexible, and is less likely detach from the contact when the contact is pulled sideways. Other embodiments are also described.

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Patent Owner(s)

  • INVENSAS CORPORATION;TRI-SI TECHNOLOGIES, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Siniaguine, Oleg San Carlos, CA 58 4144

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