Repeater for buffering a signal on a long data line of a programmable logic device
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United States of America Patent
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-
Dec 16, 2003
Grant Date -
N/A
app pub date -
Jan 22, 2002
filing date -
Jan 22, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
A configuration memory array for a programmable logic device includes an array of configuration memory cells arranged in rows and columns. Initially, each of the configuration memory cells is reset to a reset state. Each row of configuration memory cells is coupled to a corresponding data line and data line driver. During configuration, each data line driver drives a configuration data value having a first state or a second state onto the corresponding data line. A configuration data value having the first state has a polarity that tends to flip the reset state of a configuration memory cell. A repeater cell is connected to an intermediate location of each data line. Each repeater cell improves the drive of configuration data values having the first state.
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