Method of using partially defective programmable logic devices
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United States of America Patent
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Dec 16, 2003
Grant Date -
Apr 3, 2003
app pub date -
Aug 7, 2001
filing date -
Aug 7, 2001
priority date (Note) -
In Force
status (Latency Note)
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Abstract
FPGAs that contain at least one localized defect may be used to implement some designs if the localized defect is not used in the designs. To determine if the FPGA is suitable to implement a design, the design is loaded into the FPGA. The FPGA is tested to determine whether it can execute the design accurately even with the localized defect. The FPGA will be marked as suitable for that design if it passes the test. If the FPGA is found to be unsuitable for one design, additional designs may be tested. Thus, a FPGA manufacturer can sell FPGAs that are normally discarded. As a result, the price of these FPGAs could be set significantly low.
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