Importance

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Abstract

A delay circuit has a delay that is consistent under varying process and temperature conditions. The delay through a delay path is controlled by inserting resistors on the pull-up and pull-down paths of the delaying inverters. Each resistor has a resistance value that is determined by a varying a number of enabled similarly-sized transistors coupled in parallel across the resistor, rather than by varying the size of a single transistor. In one embodiment, a first transistor in each resistor is always enabled, while additional transistors are enabled using select signals. In one embodiment, the select signals are provided by configuration memory cells in a PLD. Other embodiments include additional delay paths and a multiplexer circuit that selects one of the delay paths. The described delay circuit is particularly useful in a DLL trim unit, where variations between resistors can cause jitter and locking problems in the DLL.

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First Claim