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Abstract

A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a 'asynchronous' external clock signal and external clock enable signal to an internal 'synchronous' clock signal. Input command signals are not stored in input registers, but instead are latched so as to provide such input signals rapidly downstream. Multiple redundant compare circuitry is provided to improve delays inherent in selecting between external or internal addresses. Input/output pull up circuitry is enabled during both read and write operations, but shortened during write operations. Two or more voltage pump circuits are employed that permit sharing of power therebetween to compensate for increased power demands to row lines, data output lines, etc.

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First Claim