Method and apparatus for reducing average power in RAMs by dynamically changing the bias on PFETs contained in memory cells
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United States of America Patent
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Dec 16, 2003
Grant Date -
Apr 24, 2003
app pub date -
Oct 24, 2001
filing date -
Oct 24, 2001
priority date (Note) -
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Abstract
A circuit for reducing power in SRAMS and DRAMS is implemented by dynamically controlling a voltage applied to Nwells containing PFETs used in memory cells. When a memory cell is in standby, the voltage applied to Nwells containing PFETs is increased in order to reduce leakage current. When a memory cell is being written, read, or refreshed, the voltage applied to Nwells containing PFETs is reduced in order to allow the memory cell to switch more quickly.
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