Run-time reconfigurable testing of programmable logic devices
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United States of America Patent
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Dec 23, 2003
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N/A
app pub date -
Jan 17, 2002
filing date -
Jan 17, 2002
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Abstract
Method and system for testing circuitry of a programmable logic device (PLD). A host data processing arrangement is configured with a run-time reconfiguration programming interface, and a run-time reconfiguration test program that invokes methods of the interface executes on the host arrangement. In response to a method of the programming interface invoked from the test program, the PLD is configured with a first configuration bitstream. State data are then read back from the PLD in response to a method of the programming interface invoked from the test program. The test program also identifies differences between the state data and expected-results data.
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