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Abstract

The monolithically integrated Enhancement/Depletion mode HEMT (high-electron-mobility transistor) of the present invention comprises: a buffer layer, a channel layer, a spacer layer, a first barrier layer, a second barrier layer, a third barrier layer, and an ohmic layer consecutively formed on a semiconductor substrate from bottom to top; the first exposed region (a gate region for a Depletion-mode HEMT) formed by selective etching of the ohmic layer to expose the third barrier layer; a second exposed region (a gate region for an Enhancement-mode HEMT) formed by selective etchings of the ohmic layer and the third barrier layer to expose the second barrier layer; and gate electrodes formed on the first and second exposed gate regions. According to the present invention, a monolithically integrated Enhancement/Depletion mode HEMT having a uniform threshold voltage can easily be fabricated. The second barrier layer, which has a larger bandgap energy compared with those of other barrier layers and is used for the fabrication of an Enhancement-mode HEMT, plays a role of increasing the potential barrier height with respect to the gate electrode metal. The increased potential barrier height can make the total thickness of barrier layers required for the threshold voltage of the Enhancement-mode HEMT device thicker than that of a conventional Enhancement-mode HEMT. This improves the speed characteristic of the Enhancement-mode HEMT since the transistor has a decreased gate capacitance.

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First Claim