Importance

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Abstract

An interconnect substrate includes an upper substrate (30) on which an upper interconnect pattern (32) is formed, and a lower substrate (40) on which a lower interconnect pattern (42) is formed and to which the upper substrate (30) is adhered. The lower interconnect pattern (42) includes first lower land section (53) which are formed in the center portion of a first region (50) and are connected to the upper interconnect pattern (32), second lower land sections (64) which are formed in a second region (60) and are electrically connected to a second electronic chip, and lower connection sections (45) which run outside the center portion in the first region (50) than the center portion and connect the first lower land section (53) to the second lower land section (64).

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First Claim