Device and method to test on-chip memory in a production environment
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United States of America Patent
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Dec 30, 2003
Grant Date -
N/A
app pub date -
Jun 6, 2000
filing date -
Jun 6, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A device and method to test memory embedded in a chip in which the memory is not directly accessible from a tester external to the chip. The device and method uses a state machine embedded in control circuitry of the chip to execute software to test the memory embedded on the chip. The software in turn employs a row and column address generator connected to the state machine to access each memory location in the memory embedded in the chip. A data generator is also used by the software to generate and write data to memory locations specified by the row and column address generator. Several multiplexers are used to accept data from the data generator and pass the data to the memory embedded in the chip. These multiplexers act to enable reads and writes to memory when a memory test is performed or to enable normal reads and writes to memory when normal operations of the chip are executed. A data comparator is used to determine if the memory is working properly.
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