Packet-based device test system
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United States of America Patent
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Dec 30, 2003
Grant Date -
N/A
app pub date -
Oct 19, 1999
filing date -
Oct 19, 1999
priority date (Note) -
Expired
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Abstract
A packet generator that increases the output speed of column and row addresses and data provided by a semiconductor device test system. The packet generator receives column and row addresses and data from a conventional algorithmic pattern generator (APG) and generates column and row addresses and data in packet form, thereby allowing communications with a packet-based device under test, such as a memory. The packet generator further provides variable time spacing between column and row addresses and data packets. Thereby, the packet generator advantageously allows testing of memory devices that require signal inputs at a higher rate than a conventional APG can provide.
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