Multi-instruction stream processor
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United States of America Patent
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Jan 6, 2004
Grant Date -
May 16, 2002
app pub date -
Feb 18, 1998
filing date -
Apr 30, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The present invention discloses apparatus for, and a method of, rendering image data prior to outputting of the resulting image. A graphics co-processor (224) is utilized together with a host CPU (202), the former having a plurality of data calculation streams (241, 242, 243) arranged in parallel fashion. Only one of the data calculation streams (241, 242, 243) is operated at any one time. Preferably at least one (242) of the data calculation streams is able to be reconfigured.
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