Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants
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United States of America Patent
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Jan 6, 2004
Grant Date -
Jan 24, 2002
app pub date -
Jun 11, 2001
filing date -
Jun 10, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.
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